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august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxm3aj overvoltage protector series tisp4070m3aj thru tisp4115m3aj, tisp4125m3aj thru tisp4220m3aj, tisp4240m3aj thru TISP4395M3AJ bidirectional thyristor overvoltage protectors device symbol 4 kv 10/700, 100 a 5/310 itu-t k.20/21 rating sma (do-214ac) package 25% smaller placement area than smb low differential capacitance .......................................... 39 pf ion-implanted breakdown region precise and stable voltage low voltage overshoot under surge smaj package (top view) rated for international surge wave shapes device v drm v v (bo) v ?070 58 70 ?080 65 80 ?090 68 90 ?095 75 95 ?115 90 115 ?125 100 125 ?145 120 145 ?165 135 165 ?180 145 180 ?200 155 200 ?220 160 220 ?240 180 240 ?250 190 250 ?265 200 265 ?290 220 290 ?300 230 300 ?320 240 320 ?350 275 350 ?360 290 360 ?395 320 395 mdxxcce 12 r (b) t (a) description these devices are designed to limit overvoltages on the telephone line. overvoltages are normally caused by a.c. power system o r lightning flash disturbances which are induced or conducted on to the telephone line. a single device provides 2-point protection and is typically used for the protection of 2-wire telecommunication equipment (e.g. between the ring and tip wires for telephones and modems). combi nations of devices can be used for multi-point protection (e.g. 3-point protection between ring, tip and ground). the protector consists of a symmetrical voltage-triggered bidirectional thyristor. overvoltages are initially clipped by breakd own clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. this low-voltage on s tate causes the current resulting from the overvoltage to be safely diverted through the device. the high crowbar holding current prevents d.c. latchup as the diverted current subsides. how to order t r sd4xaa t erminals t and r correspond to the alternative line designators of a and b wave shape standard i tsp a 2/10 s gr-1089-core 300 8/20 s iec 61000-4-5 220 10/160 s fcc part 68 120 10/700 s itu-t k.20/21/45 100 10/560 s fcc part 68 75 10/1000 s gr-1089-core 50 ............................................ ul recognized components device package carrier tisp 4xxxm3aj aj (j-bend do-214ac/sma) embossed tape reeled tisp4xxxm3ajr tisp4xxxm3ajr-s insert xxx value corresponding to protection voltages of 070, 080, 095, etc. for standard termination finish order as for lead free termination finish order as *rohs directive 2002/95/ec jan 27 2003 including annex *r o h s c o m p l i a n t v e r s i o n s a v a i l a b l e
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. the tisp4xxxm3aj range consists of twenty voltage variants to meet various maximum system voltage levels (58 v to 320 v). they are guaranteed to voltage limit and withstand the listed international lightning surges in both polarities. these medium (m) curren t protection devices are in a plastic package smaj (jedec do-214ac with j-bend leads) and supplied in embossed tape reel pack. for alternati ve voltage and holding current values, consult the factory. for higher rated impulse currents, the 100 a 10/1000 tisp4xxxh3bj seri es in the smb (jedec do-214aa) package is available. tisp4xxxm3aj overvoltage protector series description (continued) absolute maximum ratings, t a = 25 c (unless otherwise noted) rating symbol value unit repetitive peak off-state voltage, (see note 1) ?070 ?080 ?095 ?115 ?125 ?145 ?165 ?180 ?200 ?220 ?240 ?250 ?265 ?290 ?300 ?350 ?360 ?395 v drm 58 65 ?090 68 75 90 100 120 135 145 155 160 180 190 200 220 230 ?320 240 275 290 320 v no n-repetitive peak on-state pulse current (see notes 2, 3 and 4) i tsp a 2/10 s(gr- 1089-core, 2/10 s voltage wave shape) 300 8/20 s (iec 61000-4-5, combination wave generator, 1.2/50 voltage, 8/20 current) 220 10/160 s( f cc part 68, 10/160 s voltage wave shape) 120 5/200 s( vde 0433, 10/700 s vo ltage wave shape) 110 0.2/310 s (i3124, 0.5/700 s voltage wave shape) 100 5/310 s( it u-t k.20/21/45, k.44 10/700 s voltage wave shape) 100 5/310 s( ft z r 12, 10/700 s voltage wave shape) 100 10/560 s( f cc part 68, 10/560 s voltage wave shape) 75 10/1000 s( gr - 1089-core, 10/1000 s voltage wave shape) 50 no n-repetitive peak on-state current (see notes 2, 3 and 5) i tsm 23 24 1.6 a 20 ms (50 hz) full sine wave 16.7 ms (60 hz) full sine wave 1000 s 50 hz/60 hz a.c. in itial rate of rise of on-state current, exponential current ramp, maximum ramp value < 100 a di t /dt 300 a/ s j unction temperature t j -40 to +150 c st or age temperature range t stg -65 to +150 c no te s: 1. see applications information and figure 10 for voltage values at lower temperatures. 2. in itially, th et is p4 xx xm 3a j mu st be in thermal equilibrium with t j =25 c. 3. the surge may be repeated after the tisp4xxxm3aj returns to its initial conditions. 4. see applications information and figure 11 for current ratings at other temperatures. 5. eia/jesd51-2 environment and eia/jesd51-3 pcb with standard footprint dimensions connected with 5 a rated printed wiring tr ac k widths. see figure 9 for the current ratings at other durations. derate current values at -0.61 %/ c for ambient temperatures above 25 c.
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxm3aj overvoltage protector series electrical characteristics, t a = 25 c (unless otherwise noted) parameter t est conditions min typ max unit i drm re pe titive peak off- stat e current v d = v drm t a = 25 c t a = 85 c 5 10 a v (bo) br eakover voltage dv/dt = 250 v/ms, r sour ce = 300 ? ?070 ?080 ?095 ?115 ?125 ?145 ?165 ?180 ?200 ?220 ?240 ?250 ?265 ?290 ?300 ?350 ?360 ?395 70 80 ?090 90 95 115 125 145 165 180 200 220 240 250 265 290 300 ?320 320 350 360 395 v v (bo) impulse br eakover voltage dv/dt 1000 v/ s, linear voltage ramp, maximum ramp value = 500 v di/dt = 20 a/ s, linear current ramp, maximum ramp value = 10 a ?070 ?080 ?095 ?115 ?125 ?145 ?165 ?180 ?200 ?220 ?240 ?250 ?265 ?290 ?300 ?350 ?360 ?395 78 88 ?090 98 102 122 132 151 171 186 207 227 247 257 272 298 308 ?320 328 359 370 405 v i (bo) br eakover current dv/dt = 250 v/ms, r sour ce = 300 ? 0.15 0.6 a v t on-state voltage i t = 5a, t w = 100 s 3v i h hold ing current i t = 5a, di/dt=+/-30ma/ms 0.15 0.35 a dv/dt crit ical rate of rise of off-stat e voltage linear voltage ramp, maximum ramp value < 0.85v drm 5 kv/ s
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. thermal characteristics tisp4xxxm3aj overvoltage protector series electrical characteristics, t a = 25 c (unless otherwise noted) c off off-stat e capa citance f=1mhz, v d =1v rms, v d =0, f=1mhz, v d =1v rms, v d =-1v f=1mhz, v d =1v rms, v d =-2v f=1mhz, v d =1v rms, v d =-50v f=1mhz, v d =1v rms, v d = -100 v (s ee note 6) 4070 thru 4115 4125 thru 4220 4240 thru 4400 4070 thru 4115 4125 thru 4220 4240 thru 4395 4070 thru 4115 4125 thru 4220 4240 thru 4395 4070 thru 4115 4125 thru 4220 4240 thru 4400 4125 thru 4220 4240 thru 4395 83 62 50 78 56 45 72 52 42 36 26 19 21 15 100 74 60 94 67 54 87 62 50 44 31 22 25 18 pf note 6: to avoid possible voltage clipping, the 4125 is tested with v d =-98v. parameter t est conditions min typ max unit a i d of f-state current v d = 50 v t a = 85 c 10 parame ter test conditions min typ max unit r ja junction to free air thermal resistance eia/jesd51-3 pcb, i t = i tsm(10 00) , t a = 25 c, (see note 7) 115 c/w 265 mm x 210 mm populated line card, 4-layer pcb, i t = i tsm(1000) , t a = 25 c 52 no te 7: eia/jesd51-2 environment and pcb has standard footprint dimensions connected with 5 a rated printed wiring track widths.
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxm3aj overvoltage protector series parameter measurement information fi gure 1. voltage-current characteristic for t and r terminals all measurements are referenced to the r terminal -v v drm i drm v d i h i t v t i tsm i tsp v (bo) i (bo) i d quadrant i i switching characteristic +v +i v (bo) i (bo) v d i d i h i t v t i tsm i tsp -i quadrant iii switching characteristic pmxxaab v drm i drm
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxm3aj overvoltage protector series t ypical characteristics figure 2. off-state current vs j unction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 |i d | - off-state current - a 0?01 0?1 0? 1 10 100 tcmag v d = 50 v figure 3. normalized breakover voltage vs junction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 normalized breakover voltage 0.95 1.00 1.05 1.10 tc4maf figure 4. on-state current vs on-state voltage v t - on-state voltage - v 0.7 1.5 2 3 4 5 7 1110 i t - on-state current - a 1.5 2 3 4 5 7 15 20 30 40 50 70 1 10 100 t a = 25 c t w = 100 s tc4macc '4240 thru '4395 '4125 thru '4200 '4070 thru '4115 figure 5. normalized holding current vs junction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 normalized hol ding current 0.4 0.5 0.6 0.7 0.8 0.9 1.5 2.0 1.0 tc4mad
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxm3aj overvoltage protector series t ypical characteristics figure 6. normalized capacitance vs off-state voltage v d - of f-state voltage - v 0.5 1 2 3 5 10 20 30 50 100 150 capacitance normal i zed to v d = 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t j = 25 c v d = 1 vrms tc4mabc ' 4240 t hru '4395 ' 4125 t hru ' 4200 ' 4070 t hru '4115 figure 7. differential off-state capacitance vs ra te d r epetitive peak off-state voltage v drm - re petitive peak off-state voltage - v 50 60 70 80 90 150 200 250 300 350 100 ? ? ? ? c - different ial off-state capacitance - pf 20 25 30 35 40 ? ? ? ? c = c off (-2 v) - c off (-50 v ) tcmaeb figure 8. typical capacitance asymmetry vs off-state voltage v d ?off- state voltage v 0.5 0.7 2 3 4 5 7 20 30 4050 110 |c off(+vd) - c off(-vd) | ? capaci tance asymmetr y pf 0 1 2 3 v d = 1 v rms, 1 mhz v d = 10 mv rms, 1 mhz tc4xbb
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxm3aj overvoltage protector series rating and thermal information figure 9. non-repetitive peak on-state current vs current duration t - current duration - s 0? 1 10 100 1000 i tsm(t) - non-repetitive peak on-state current - a 1.5 2 3 4 5 6 7 8 9 15 20 10 ti4mal v gen = 600 vrms, 50/60 hz r gen = 1.4*v gen / i tsm(t) ei a/jesd51-2 environment ei a/jesd51-3 pcb t a = 25 c figure 10. v drm derating factor vs minimum ambient temperature t amin - mi nimum ambient temperature - c -35 -25 -15 -5 5 15 25 -40 -30 -20 -10 0 10 20 derating factor 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 ti4madab ' 412 5 thr u ' 4200 ' 4240 thru '4395 ' 4070 thru '4115 figure 11. impulse rating vs ambient temperature t a - am bient temperature - c -40 -30 -20 -10 0 10 2 0304050607080 impulse current - a 40 50 60 70 80 90 100 120 150 200 250 300 400 iec 1.2/50, 8/20 itu-t 10/700 fcc 10/560 bellcore 2/10 bellcore 10/1000 fcc 10/160 tc4maa
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxm3aj overvoltage protector series these devices are two terminal overvoltage protectors. they may be used either singly to limit the voltage between two conducto rs (figure 12) or in multiples to limit the voltage at several points in a circuit (figure 13). applications information deployment impulse testing to verify the withstand capability and safety of the equipment, standards require that the equipment is tested with various imp ulse wave forms. the table below shows some common values. in figure 12, protector th1 limits the maximum voltage between the two conductors to v (bo) . this configuration is normally used to protect circuits without a ground reference, such as modems. in figure 13, protectors th2 and th3 limit the maximum voltage between eac h conduc- tor and ground to the v (bo) of the individual protector. protector th1 limits the maximum voltage between the two conductors to its v (bo) value. if the equipment being protected has all its vulnerable components connected between the conductors and ground, then pro tector th1 is not required. if the impulse generator current exceeds the protectors current rating, then a series resistance can be used to reduce the cur r ent to the protectors rated value to prevent possible failure. the required value of series resistance for a given waveform is given by t he following calculations. first, the minimum total circuit impedance is found by dividing the impulse generators peak voltage by the prote ctors rated current. the impulse generators fictive impedance (generators peak voltage divided by peak short circuit current) is then sub tracted from the minimum total circuit impedance to give the required value of series resistance. for the fcc part 68 10/560 waveform, the following values result. the minimum total circuit impedance is 800/75 = 10.7 ? and the generators fictive impedance is 800/100 = 8 ? . this gives a minimum series resistance value of 10.7 - 8 = 2.7 ? . after allowing for tolerance, a 3 ? 10% r esistor would be suitable. the 10/160 waveform needs a standard resistor value of 5.6 ? per conductor. these would be r1a and r1b in figure 15 and figure 16. fcc part 68 allows the equipment to be non-operational after the 10/160 (conductor to ground) and 10/5 60 (inter- conductor) impulses. the series resistor value may be reduced to zero to pass fcc part 68 in a non-operational mode, e.g. figur e 14. for this type of design, the series fuse must open before the tisp4xxxm3 fails. for figure 14, the maximum fuse i 2 t is 2.3 a 2 s. in some cases, the equipment will require verification over a temperature range. by using the rated waveform values from figure 11, the appropriat e series resistor value can be calculated for ambient temperatures in the range of -40 c to 85 c. fi gure 12. two point protection th1 figure 13. multi-point protection th3 th2 th1 standard p eak voltage setting v vo ltage wave shape s p eak current value a current wave shape s tisp4xxxm3 25 c ra ting a series resistance ? gr-1089-core 2500 2/10 500 2/10 300 11 1000 10/1000 100 10/1000 50 f cc part 68 (march 1998) 1500 10/160 200 10/160 120 2x5.6 800 10/560 100 10/560 75 3 1500 9/720 ? 37.5 5/320 ? 100 0 1000 9/720 ? 25 5/320 ? 100 0 i3124 1500 0.5/700 37.5 0.2/310 100 0 itu-t k.20/k.21 1500 4000 10/700 37.5 100 5/310 100 0 ? fcc part 68 terminology for the waveforms produced by the itu-t recommendation k.21 10/700 impulse generator
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. the protector characteristic off-state capacitance values are given for d.c. bias voltage, v d , values of 0, -1 v, -2 v and -50 v. where possible values are also given for -100 v. values for other voltages may be calculated by multiplying the v d = 0 capacitance value by the factor given in figure 6. up to 10 mhz, the capacitance is essentially independent of frequency. above 10 mhz, the effective capacitance is str ongly dependent on connection inductance. in many applications, such as figure 15 and figure 17, the typical conductor bias voltages will be about -2 v and -50 v. figure 7 shows the differential (line unbalance) capacitance caused by biasing one protector at -2 v and the ot her at -50 v. figure 8 shows the typical capacitance asymmetry; the difference between the capacitance measured with a positive value of v d and the capacitance value when the polarity of v d is reversed. capacitance asymmetry is an important parameter in adsl systems where the protector often has no d.c. bias and the signal level is in the region of 10 v. the protector can withstand currents applied for times not exceeding those shown in figure 9. currents that exceed these times must be terminated or reduced to avoid protector failure. fuses, ptc (positive temperature coefficient) thermistors and fusible resisto rs are overcurrent protection devices which can be used to reduce the current flow. protective fuses may range from a few hundred milliamperes to one ampere. in some cases, it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. the current versus time characteristic of the overcurrent protector must be below the line shown in figure 9. in some cases, there may be a furthe r time limit imposed by the test standard (e.g. ul 1459 wiring simulator failure). tisp4xxxm3aj overvoltage protector series ac power testing capacitance normal system voltage levels the protector should not clip or limit the voltages that occur in normal system operation. for unusual conditions, such as ring ing without the line connected, some degree of clipping is permissible. under this condition, about 10 v of clipping is normally possible witho ut activating the ring trip circuit. figure 10 allows the calculation of the protector v drm value at temperatures below 25 c. the calculated value should not be less than the maximum normal system voltages. the tisp4265m3aj, with a v drm of 200 v, can be used for the protection of ring generators producing 100 v rms of ring on a battery voltage of -58 v (th2 and th3 in figure 17). the peak ring voltage will be 58 + 1.414*100 = 199. 4 v. however, this is the open circuit voltage and the connection of the line and its equipment will reduce the peak voltage. in the extreme case of an unconnected line, clipping the peak voltage to 190 v should not activate the ring trip. this level of clipping would occur at t he temperature when the v drm has reduced to 190/200 = 0.95 of its 25 c value. figure 10 shows that this condition will occur at an ambient temperature of -28 c. in this example, the tisp4265m3aj will allow normal equipment operation provided that the minimum expected ambient temperatu re does not fall below -28 c. jesd51 thermal measurement method to standardize thermal measurements, the eia (electronic industries alliance) has created the jesd51 standard. part 2 of the st andard (jesd51-2, 1995) describes the test environment. this is a 0.0283 m 3 (1 ft 3 ) cube which contains the test pcb (printed circuit board) horizontally mounted at the center. part 3 of the standard (jesd51-3, 1996) defines two test pcbs for surface mount components; one for packages smaller than 27 mm on a side and the other for packages up to 48 mm. the smbj measurements used the smaller 76.2 mm x 114.3 mm (3.0 ?x 4.5 ? pcb. the jesd51-3 pcbs are designed to have low effective thermal conductivity (high thermal resistanc e) and r epresent a worst case condition. the pcbs used in the majority of applications will achieve lower values of thermal resistance , and can dissipate higher power levels than indicated by the jesd51 values.
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxm3aj overvoltage protector series t ypical circuits fi gu re 14. modem inter-wire protection fuse tisp4350 ai6xbma ring detector hook switch d.c. sink signal modem ring tip fi g ure 15. protection module r1a r1b ring wire tip wire th3 th2 th1 protected equipment e.g. li ne card ai6xbk figure 16. isdn protection r1a r1b th3 th2 th1 ai6xbl signal d.c. figure 17. line card ring/test protection test relay ring relay slic relay test equip- ment ring generator s1a s1b r1a r1b ring wire tip wire th3 th2 th1 th4 th5 slic slic protection ring/test protection over- current protection s2a s2b s3a s3b v bat c1 220 nf ai6xbj tisp6xxxx, tisppblx, 1/2tisp6ntp2
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical data tisp4xxxm3aj overvoltage protector series recommended printed wiring footprint device symbolization code devices will be coded as below. as the device parameters are symmetrical, terminal 1 is not identified. carrier information for production quantities, the carrier will be embossed tape reel pack. evaluation quantities may be shipped in bulk pack or em bossed tape. sm a land pattern mdxx bic 2.34 (. 092) 1.90 (. 075) 2.16 (.08 5) dimensions are: millimeters (inches) device symbolization code tisp4070m3aj 4070m3 tisp4080m3aj 4080m3 tisp4095m3aj 4095m3 tisp4115m3aj 4115m3 tisp4125m3aj 4125m3 tisp4145m3aj 4145m3 tisp4165m3aj 4165m3 tisp4180m3aj 4180m3 tisp4200m3aj 4200m3 tisp4220m3aj 4220m3 tisp4240m3aj 4240m3 tisp4250m3aj 4250m3 tisp4265m3aj 4265m3 tisp4290m3aj 4290m3 tisp4300m3aj 4300m3 tisp4350m3aj 4350m3 tisp4360m3aj 4360m3 TISP4395M3AJ 4395m3 tisp4090m3aj 4090m3 ca rrier standard quantity embossed tape reel pack 5,000
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical data tisp4xxxm3aj overvoltage protector series smaj (do-214ac) plastic surface mount diode package this surface mount package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. the compou nd will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated i n high humidity conditions. leads require no additional cleaning or processing when used in soldered assembly. sma mdxxcaa 2 index mark (if needed) 2.29 - 2.92 (.090 - .115) 4.06 - 4.57 (.160 - .180) 2.00 - 2.40 (.079 - .095) 0.76 - 1.52 (.030 - .060) 4.83 - 5.59 (.190 - .220) 1.58 - 2.16 (.062 - .085) 0.10 - 0.20 (.004 - .008) 1.27 - 1.63 (.050 - .064) dimensions are: millimeters (inches)
august 2001 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical data tisp4xxxm3aj overvoltage protector series t ape dimensions mdxxcga sma package single-sprocket tape carrier tape embossment direction of feed maximum component r otation t ypical component cavity center line t ypical component center line index mark (if needed) cover t ape 20 3.90 - 4.10 (.154 - .161) 11.70 - 12.30 (.461 - .484) 5.45 - 5.55 (.215 - .219) 1.5 (.059) min. 0 min. 4.50 (.177) max. 8.20 (.323) max. 0.40 (.016) max. 1.65 - 1.85 (.065 - .073) 1.55 - 1.65 (.061 - .065) 1.95 - 2.05 (.077 - .081) 3.90 - 4.10 (.154 - .161) notes: a. the clearanc e between the component and the cavity must be within 0.05 mm (.002 in) min. to 0.65 mm (.026 in) max. so that the component cannot rotate more than 20 within the determined cavity. b. tape d devices are supplied on a reel of the following dimensions: reel diameter: 330 mm 3.0 mm (12.99 in .12 in ) reel hub di ameter: 75 mm (2.95 in) min. reel axia l hole: 13.0 mm 0.5 mm (.51 in .02 in) c. 5000 devices per reel. dimensions are: millimeters (inches) ?isp?is a trademark of bourns, ltd., a bourns company, and is registered in u.s. patent and trademark office. ?ourns?is a registered trademark of bourns, inc. in the u.s. and other countries.

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